In some integrated circuit applications, a single device can receive multiple clock signals and select one clock signal for performing internal circuit functions. Such devices can include a clock selection circuit for selecting between multiple clock signals based on predetermined criteria. One such application can occur in dual ported memory devices or systems. In such applications, multiple clock signals can be received and the faster of the clock signals can be selected for the timing of an internal memory core.
In order to provide the flexibility of connecting any one of the ports to any of the clock domains without reconfiguring the memory device, a circuit or logic can be included on the memory device that can select the faster clock.
A conventional approach for detecting a faster of two clock signals is shown in FIG. 9, and designated by the general reference character 900. The conventional approach shows an “overflow” method. In the conventional overflow method shown, a clock detection/selection circuit 900 can include two counters 902-0 and 902-1, each operating in a different clock domain. Thus, counter 902-0 operates in a first clock domain (based on a first clock signal CLK1), while counter 902-1 operates in a second clock domain (based on a second clock signal CLK2). Counters (902-0 and 902-1) can be Gray Code counters.
Each counter (902-0 and 902-1) can generate a count value based on its respective clock signal (CLK1 and CLK2). Count values from counters 902-0 and 902-1, can be provided to overflow detectors 904-0 and 904-1, respectively. The faster of the two clock signals (CLK1 and CLK2) can be determined by detecting an overflow condition. An overflow condition can be detected by examining the most significant bit of each counter (902-0 and 902-1). Whichever counter reaches an overflow condition first, can be considered the faster clock.
A faster clock signal can be selected based on the overflow information by select logic 906. Such a faster clock can be utilized to time the operations of another circuit, such as a core portion of a dual-port random access memory (RAM).
Both counter 902-1 and overflow detector 904-1 can operate in one clock domain (e.g., based on clock CLK2), while the other components can operate in a different clock domain (e.g., based on clock CLK1). Thus, to ensure appropriate timing between signals generated in the different clock domains, output signals from overflow detector 904-1 can be provided to other circuit components by way of a synchronizer 908.
The bit size of the counters (902-0 and 902-1) can be selected according to expected deviation between clock signals, typically expressed in parts per million (ppm) from a center frequency.
While the above-described approach can select the faster of two clock signals, the above circuit can have disadvantages. In the event the two clocks differ in frequency by a very small amount, detection of the fastest clock can take a significant amount of time. For example if the device is designed to detect the faster clock of two clocks having a difference of 20 ppm, one clock cycle difference will occur after 50,000 cycles. Thus, a counter overflow method would require a 16-bit counter. Counting 64K clock cycles can present a significant amount of time before a fastest clock can be selected.
Still further, using the same conventional example above, the time required to determine a faster clock signal can get even more significant in a system where the difference between the two clocks from each other is smaller. For a 10 ppm difference, 100K clock cycles are required. Even in cases where the clock difference is larger, the overflow method requires waiting until an overflow of the fastest clock. So, even if one clock is twice as fast as the other clock, it will still require 64K cycles of the faster clock to arrive at a fastest clock determination.
In light of the above, it would be desirable to arrive at one way of detecting the faster of multiple clock signals that does not introduce the substantial counting delay noted above.
In addition, it would be desirable to arrive at a multiported memory device having logic or other circuitry for detecting the faster of multiple clock signals, and using a faster clock signal to run the internal core timing of the memory device.